In communications chips, there is usually some kind of clock and data recovery (CDR) circuit, which recovers clock and data signals based on packetized data. As the complexities of the data packets increase and data packet transfer rates increase, the complexity of the state machine logic also increases. The state machine logic must qualify and decode the data packets. This increased complexity makes it difficult to avoid all potential clock glitches.
FIGS. 1 and 2 show conventional CDR technology, for example, as discussed in U.S. Pat. No. 6,535,023. In particular, FIG. 1 shows a block diagram of the conventional CDR circuit and FIG. 2 shows a more detailed view of a conventional digital phase detector and digital filter used in the CDR circuit. Such conventional CDR technology uses relative phase error sampling. Relative phase sampling refers to the use of the clock signal and a number of relative phase signals that are chosen depending on which phase signal is selected as the clock signal at the time of phase error sampling. In order to properly function, relative phase error sampling requires an absolute reference phase in order to start the system and lock on to a new data signal. For example, phase 0 may be chosen from phases 0-7 to serve as the absolute reference phase. In order to use the absolute reference phase at the start of packet (SOP) of a new data packet, the clock is typically reset to the absolute reference phase at the end of packet (EOP) of the previous data packet. Unfortunately, resetting the clock signal at the EOP may cause a clock glitch, or non-linearity, and result in an invalid state in a downstream state machine.
In addition, conventional CDR technology uses only two loop filter modes: acquisition and tracking. Acquisition mode, or high bandwidth mode, refers to the mode in which the conventional CDR circuit initially synchronizes the clock signal with the data signal of a new data packet. Tracking mode, or low bandwidth mode, refers to the mode in which the conventional CDR circuit adjusts the clock signal while the data packet is being received in order to maintain synchronization of the clock signal with the data signal of the data packet. By using only two modes, the conventional CDR circuit reverts from the tracking mode back to the acquisition mode at the EOP, adjusting the clock signal to the absolute reference phase, until a new data packet is detected. Unfortunately, the conventional CDR circuit is unable to implement a hold mode in which the clock signal remains unchanged at the EOP, thus, allowing EOP operations to occur without a clock glitch.